1. Field of the Invention
The present invention relates to a semiconductor device and more particularly relates to a semiconductor device in which the upper surfaces of storage-node contact plugs and the upper surfaces of peripheral contact plugs are located in the same plane.
2. Description of Prior Art
A semiconductor device such as a DRAM (Dynamic Random Access Memory) has a memory cell area and a peripheral circuit area formed on a principal surface of a semiconductor substrate. The memory cell area includes a plurality of memory cells each having a cell transistor and a storage node. The peripheral circuit area includes various peripheral circuits for performing operations such as read operation and write operation to the memory cells in the memory cell area.
Japanese Patent Application Laid-open No. 2012-99793 discloses a specific example of a structure of cell transistors included in memory cells and a structure of peripheral transistors formed in a peripheral circuit area.
In a semiconductor device described in Japanese Patent Application Laid-open No. 2012-99793, a first interlayer insulating film 33 is formed on a surface of a semiconductor substrate that embeds bit lines 30, capacitor contact plugs 34 (storage-node contact plugs), and source/drain contact plugs 34a (peripheral contact plugs). The capacitor contact plugs 34 are used to connect source/drain electrodes of the cell transistors to lower electrodes 35 of cell capacitors. The source/drain contact plugs 34a are used to connect source/drain electrodes of the peripheral transistors to an upper layer wiring 35a. A cover insulating film 28 and a side-wall insulating film 31a cover the upper and side surfaces of the bit lines 30, respectively. The cover insulating film 28 and the side-wall insulating film 31a are also entirely embedded in the first interlayer insulating film 33. Although not described in detail in Japanese Patent Application Laid-open No. 2012-99793, a manufacturing procedure from formation of the bit lines 30 to formation of the lower electrodes 35 in the semiconductor device having the above structure may be as follows.
That is, a conductive film and an insulating film are first formed in this order and then these films are patterned to obtain the bit lines 30 and the cover insulating film 28. Another insulating film is then formed on the entire surface and is etched back to form the side-wall insulating film 31a. The first interlayer insulating film 33 is then formed in a thickness to cover the cover insulating film 28. The upper surface of the first interlayer insulating film 33 is flattened, and then through holes for embedding therein the capacitor contact plugs 34 and the source/drain contact plugs 34a are provided in the first interlayer insulating film 33. A conductive film is formed in a thickness to fill the through holes. Then the surface is flattened so as to expose the upper surface of the first interlayer insulating film 33 to form the capacitor contact plugs 34 and the source/drain contact plugs 34a. 
A conductive film is then formed again and is patterned to form the wiring 35a having the lower surface that is in contact with the source/drain contact plugs 34a on the upper surface of the first interlayer insulating film 33. An insulating film that covers the wiring 35a is further formed on the entire surface. Through holes passing through the insulating film are formed, and then the inner surfaces of the through holes are covered with a conductive film to form the lower electrodes 35 having the lower surfaces that are in contact with the capacitor contact plugs 34.
However, the above manufacturing procedure has a problem that, at the time of formation of the wiring 35a, the capacitor contact plugs 34 may be damaged. Also the insulating film (the cover insulating film 28 and the first interlayer insulating film 33) covering the upper surfaces of the bit lines 30 is reduced in the thickness, which adversely reduces a short margin between the bit lines 30 and a silicon oxide film. This is because the capacitor contact plugs 34 and the insulating film that covers the upper surfaces of the bit lines 30 are subjected to an etching condition to form the wiring 35a. That is, because the thickness of the conductive film or the etching speed is not completely uniform in the surface, the etching is continued in a certain area even after the wiring 35a is completely removed when the conductive film is patterned to form the wiring 35a. On the surface from which the wiring 35a has been completely removed, the capacitor contact plugs 34 and the insulating film that covers the upper surfaces of the bit lines 30 are exposed and thus subjected to an etching condition. As a result, the problem as mentioned above occurs.